module nct_arr_8881( Z, X, Y);
input [7:0] Y;
input [7:0] X;
output [7:0] Z;
wire [1] zero =0 ;
wire [1] one =1 ;
wire [1] P0_7 = X[7] & Y[0];
wire [1] P0_6 = X[6] & Y[0];
wire [1] sum1_7 = X[7] & Y[1];
wire [1] P1_6 = X[6] & Y[1];
wire [1] P1_5 = X[5] & Y[1];
wire [1] sum2_7 = X[7] & Y[2];
wire [1] P2_6 = X[6] & Y[2];
wire [1] P2_5 = X[5] & Y[2];
wire [1] P2_4 = X[4] & Y[2];
wire [1] sum3_7 = X[7] & Y[3];
wire [1] P3_6 = X[6] & Y[3];
wire [1] P3_5 = X[5] & Y[3];
wire [1] P3_4 = X[4] & Y[3];
wire [1] P3_3 = X[3] & Y[3];
wire [1] sum4_7 = X[7] & Y[4];
wire [1] P4_6 = X[6] & Y[4];
wire [1] P4_5 = X[5] & Y[4];
wire [1] P4_4 = X[4] & Y[4];
wire [1] P4_3 = X[3] & Y[4];
wire [1] P4_2 = X[2] & Y[4];
wire [1] sum5_7 = X[7] & Y[5];
wire [1] P5_6 = X[6] & Y[5];
wire [1] P5_5 = X[5] & Y[5];
wire [1] P5_4 = X[4] & Y[5];
wire [1] P5_3 = X[3] & Y[5];
wire [1] P5_2 = X[2] & Y[5];
wire [1] P5_1 = X[1] & Y[5];
wire [1] sum6_7 = X[7] & Y[6];
wire [1] P6_6 = X[6] & Y[6];
wire [1] P6_5 = X[5] & Y[6];
wire [1] P6_4 = X[4] & Y[6];
wire [1] P6_3 = X[3] & Y[6];
wire [1] P6_2 = X[2] & Y[6];
wire [1] P6_1 = X[1] & Y[6];
wire [1] P6_0 = X[0] & Y[6];
wire [1] sum7_7 = X[7] & Y[7];
wire [1] P7_6 = X[6] & Y[7];
wire [1] P7_5 = X[5] & Y[7];
wire [1] P7_4 = X[4] & Y[7];
wire [1] P7_3 = X[3] & Y[7];
wire [1] P7_2 = X[2] & Y[7];
wire [1] P7_1 = X[1] & Y[7];
wire [1] P7_0 = X[0] & Y[7];
